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1 ? fn9283.1 isl8106 wide vin, 7v to 25v, single-phase pwm controller with integrated mosfet drivers the isl8106 is a single-phase synchronous-buck pwm controller with a input voltage range of +7.0v to +25.0v featuring intersil's robust ripple regulator (r 3 ) technology that delivers exceptional dynamic response to input voltage and output load transients. in tegrated mosfet drivers, 5v ldo, and bootstrap diode result in fewer components and smaller implementation area for power supply systems. the isl8106 features a 1.5ms di gital soft-start and can be started into a pre-biased output voltage. a resistor divider is used to program the output voltage setpoint. the isl8106 can be configured to operate in forced-continuous- conduction-mode (fccm) or in diode-emulation-mode (dem), which improves light-load efficiency. in fccm the controller always operates as a synchronous rectifier, switching the bottom-side mosf et regardless of the output load. with dem enabled, the bottom-side mosfet is disabled preventing negative current flow from the output inductor during low load operation. this makes the isl8106 an excellent choice for all ?green? applications. an audio filter prevents the pwm switch ing frequency from entering the audible spectrum due to extremely light load while in dem. a pgood pin featuring a uni que fault-identification capability significantly reduce s system trouble-shooting time and effort. the pull-down resistance of the pgood pin is 30 for an overcurrent fault, 60 for an overvoltage fault, or 90 for either an undervoltage fault or during soft-start. overcurrent protection is accomplished by measuring the voltage drop across the r ds(on) of the bottom-side mosfet. a single resistor programs the overcurrent and short-circuit points. overvoltage and undervoltage protection is monitored at the fb voltage feedback pin. pinout 16 ld qfn (4mm x 4mm) top view features ? wide input voltage range: +7.0v to +25.0v ? high performance r 3 technology delivers extremely fast transient response ? +0.6v internal reference - 0.6% tolerance over the commercial temperature range (0c to +70c) - 1.0% tolerance over the in dustrial temperature range (-40c to +85c) ? output voltage range: +0.6v to v cc -0.3v ? selectable forced continuous conduction mode or diode emulation mode ? integrated mosfet drivers with shoot-through protection ? external type-two loop compensation ? internal 5v low-dropout re gulator with integrated boot- strap diode ? programmable pwm frequency: 200khz to 600khz ? pwm minimum frequency above audible spectrum ? internal digital soft-start wi th prebiased startup capability ? power good monitor with fault identification by pgood pull down resistance ? lossless, programmable overcurrent protection - uses bottom-side mosfet?s r ds(on) ? undervoltage protection, soft crowbar overvoltage protection and over-temperature protection ? pb-free plus anneal available (rohs compliant) applications ? telecom/datacom applications ? industrial applications ? distributed dc/dc power architecture ? point-of-load modules 1 3 4 15 16 14 13 2 12 10 9 11 6 578 gnd boot pgood tgate lx vo comp fset fb bsoc pvcc pgnd bgate en vin fccm vcc data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. november 10, 2006
2 fn9283.1 november 10, 2006 typical application ordering information part number part marking temp (c) package pkg. dwg. # isl8106crz* 8106crz 0 to +70 16 ld 4x4 qfn l16.4x4 isl8106irz* 8106irz -40 to +85 16 ld 4x4 qfn l16.4x4 isl8106eval1z evaluation board *add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl8106 c out vin tgate lx q ts bsoc q bs bgate pgnd fset pgood pvcc vcc gnd fccm en comp fb r bsoc c in boot cboot c fset r fset vo r bot r top c comp1 c comp2 r comp c vcc r vcc r pgood c pvcc pgood l out v in +7v to +25v v out isl8106
3 fn9283.1 november 10, 2006 isl8106 block diagram v w v r pwm r pgood en fb comp bsoc boot tgate bgate pvcc pgnd fccm lx uvp s q por digital soft-start 150ot shoot through protection driver driver v comp pwm control vin fset vcc vo v ref ldo + ? ovp + ? ea ? + ea ocp + ? ? + g m v in ? + g m v o ? + ? + ? + c r pwm frequency control gnd package bottom i oc 30 90 60 ? +
4 fn9283.1 november 10, 2006 absolute voltage ratings bsoc, vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v vcc, pgood to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v pvcc to pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v gnd to pgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v en, fccm. . . . . . . . . . . . . . . . . . . . . . . . -0.3v to gnd, vcc +3.3v lx to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (dc) -0.3v to +28v . . . . . . . . . . . . . . . . . . . . . . . . . . (<100ns pulse width, 10 j) -5.0v boot to gnd, or pgnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v tgate . . . . . . . . . . . . . . . . . . . . . . .(dc) -0.3v to lx, boot +0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . (<200ns pulse width, 20 j) -4.0v bgate . . . . . . . . . . . . . . . . . . . . (dc) -0.3v to pgnd, pvcc +0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . (<100ns pulse width, 4 j) -2.0v esd classification . . . . . . . . . . . . . . . . . . . . . .level 1 (hbm = 2kv) thermal information thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) qfn package . . . . . . . . . . . . . . . . . . . 48 11.5 junction temperature range . . . . . . . . . . . . . . . . . -55 c to +150 c operating temperature range isl8106crz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c isl8106irz . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65 c to +150 c lead temperature . . . . . . . . . . . . . . . . . . . . (soldering, 10s)+300 c recommended operating conditions ambient temperature range (isl8106c) . . . . . . . . . . 0c to +70c ambient temperature range (isl8106i) . . . . . . . . . -40c to +85c supply voltage (vin to gnd) . . . . . . . . . . . . . . . . . . . . . . 7v to 25v caution: stress above those listed in ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in th e operational section of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. parameters are guaranteed by design. electrical specifications recommended operating conditions, unless otherwise noted specifications in bold are valid for process, temperature, and line operating conditions. parameter symbol test conditions min typ max unit vin vin voltage range v in 7.0 25.0 v vin input bias current i vin en and fccm = 5v, fb = 0.65v, vin = 7v to 25v 2.2 3.0 ma vin shutdown current i shdn en = gnd, vin = 25v 0.1 1.0 a vcc ldo vcc output voltage range v cc vin = 7v to 25v, i ldo = 0ma to 80ma 4.75 5.00 5.25 v vcc por threshold rising vcc por threshold voltage v ccthr isl8106crz 4.35 4.45 4.55 v isl8106irz 4.33 4.45 4.55 v falling vcc por threshold voltage v ccthf isl8106crz 4.10 4.20 4.30 v isl8106irz 4.08 4.20 4.30 v control inputs en high threshold voltage v enthr 2.0 v en low threshold voltage v enthf 0.5 v fccm high threshold voltage v fccmthr 2.0 v fccm low threshold voltage v fccmthf 1.0 v en leakage current i enl en = 0v <0.1 1.0 a i enh en = 5.0v 20 a fccm leakage current i fccml fccm = 0v <0.1 1.0 a i fccmh fccm = 5.0v 2.0 a reference reference voltage v ref 0.6 v voltage regulation accuracy v reg isl8106crz -0.6 +0.6 % isl8106irz -1.0 +1.0 % isl8106
5 fn9283.1 november 10, 2006 pwm frequency range f osc fccm = 5v 200 600 khz f audio fccm = gnd; isl8106crz 21 28 khz fccm = gnd; isl8106irz 20 28 khz frequency-set accuracy f osc = 300khz; isl8106crz -10 +10 % f osc = 300khz; isl8106irz -12 +12 % vo range v vo 0.60 3.30 v vo input leakage current i vo vo = 0.60v vo = 3.30v 1.3 7.0 a a error amplifier fb input bias current i fb fb = 0.60v 20 na comp source current i compsrc fb = 0.40v, comp = 3.20v 2.5 ma comp sink current i compsnk fb = 0.80v, comp = 0.30v 0.3 ma comp high clamp voltage v comphc fb = 0.40v, sink 50 a 3.10 3.40 3.65 v comp low clamp voltage v complc fb = 0.80v, source 50 a 0.09 0.15 0.21 v gate driver tgate pull-up resistance r tgatepu 200ma source current (note 3) 1.0 1.5 tgate source current i tgatesrc v tgate to lx = 2.5v 2.0 a tgate sink resistance r tgatepd 250ma sink current (note 3) 1.0 1.5 tgate sink current i tgatesnk v tgate to lx = 2.5v 2.0 a bgate pull-up resistance r bgatepu 250ma source current (note 3) 1.0 1.5 bgate source current i bgatesrc v bgate to pgnd = 2.5v 2.0 a bgate sink resistance r bgatepd 250ma sink current (note 3) 0.5 0.9 bgate sink current i bgatesnk v bgate to pgnd = 2.5v 4.0 a delay from tgate falling to bgate rising t tgatefbg ater tgate falling to bgate rising 21 ns delay from bgate falling to tgate rising t bgateftg ater bgate falling to tgate rising 14 ns bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma 0.58 v reverse leakage i r v r = 25v 0.2 a power good pgood pull down impedance pgr ss pgood = 5ma sink; isl8106crz 75 95 115 pgr uv pgr ss pgood = 5ma sink; isl8106irz 67 95 118 pgr uv pgr ov pgood = 5ma sink; isl8106crz 50 63 78 pgood = 5ma sink; isl8106irz 45 63 81 pgr oc pgood = 5ma sink; isl8016crz 25 32 40 pgood = 5ma sink; isl8106irz 22 32 43 pgood leakage current i pgood pgood = 5v <0.1 1.0 a pgood maximum sink current 5.0 ma electrical specifications recommended operating conditions, unless otherwise noted specifications in bold are valid for process, temperature, and line operating conditions. parameter symbol test conditions min typ max unit isl8106
6 fn9283.1 november 10, 2006 functional pin descriptions gnd (bottom terminal pad) signal common of the ic. unless otherwise stated, signals are referenced to the gnd pi n, not the pg nd pin. connect the gnd pad of the isl8106 to the signal ground layer of the pcb using at least five vias, for a robust thermal and electrical conduction path. the best tie-point between the signal ground and the power ground is at the negative side of the output capacitors that is not in the return path of the inductor ripple current flowing through the output capacitors. vin (pin 1) the vin pin measures the converter input voltage with respect to the gnd pin. vin is a required input to the r 3 pwm modulator. the vin pin is al so the input source for the integrated +5v ldo regulator. vcc (pin 2) the vcc pin is the output of th e integrated +5v ldo regulator, which provides the bias voltage for the ic. the vcc pin delivers regulated +5v whenever the en pin is pulled above v enthr . for best performance, the ldo requires at least a 1f mlcc decouple capacitor to the gnd pin. fccm (pin 3) the fccm pin configures the cont roller to operate in forced- continuous-conduction-mode (fccm) or diode-emulation- mode (dem). dem is disabled when the fccm pin is pulled above the rising threshold voltage v fccmthr , and dem is enabled when the fccm pin is pulled below the falling threshold voltage v fccmthf. en (pin 4) the en pin is the on/off switch of the ic. when the en pin is pulled above the rising threshold voltage v enthr, v cc will ramp up and begin regulation. the soft-start sequence begins once v cc ramps above the power-on reset (por) rising threshold voltage v ccthr . when the en pin is pulled below the falling threshold voltage v enthf , pwm immediately stops and v cc decays below the por falling threshold voltage v ccthf , at which time the ic turns off. comp (pin 5) the comp pin is the output of the control-loop error amplifier. loop compensation components connect from the comp pin to the fb pin. fb (pin 6) the fb pin is the inverting input of the control loop error amplifier. the converter will re gulate to 600mv at the fb pin with respect to the gnd pin. scale the desired output voltage to 600mv with a voltage divider network made from resistors r top and r bottom . loop compensation components connect from the fb pin to the comp pin. fset (pin 7) the fset pin programs the pwm switching frequency of the converter. connect a resistor r fset and a 10nf capacitor c fset from the fset pin to the gnd pin. vo (pin 8) the vo pin makes a direct measurement of the converter output voltage used exclusively by the r 3 pwm modulator. the vo pin should be connected to the top of feedback resistor r top at the converter output. refer to typical application schematic. bsoc (pin 9) the bsoc pin is the input to the overcurrent protection (ocp) and short-circuit protection (scp) circuits. connect a resistor r bsoc between the bsoc pin and the lx pin. select the value of r bsoc that will force the bsoc pin to source the i bsoc threshold current i oc when the peak inductor current reaches the desired ocp setpoint. the scp threshold current i sc is fixed at twice the ocp threshold current i oc . pgood soft-start delay t ss en high to pgood high; isl8106crz 2.20 2.75 3.30 ms en high to pgood high; isl8106irz 2.20 2.75 3.50 ms protection bsoc ocp threshold current i oc isl8106crz -33 -26 -19 a isl8106irz -33 -26 -17 a bsoc short-circuit threshold current i sc -50 a uvp threshold voltage v uv 81 84 87 % ovp rising threshold voltage v ovr 113 116 119 % ovp falling threshold voltage v ovf 103 % otp rising threshold temperature t otr (note 3) 150 c otp temperature hysteresis t othys (note 3) 25 c electrical specifications recommended operating conditions, unless otherwise noted specifications in bold are valid for process, temperature, and line operating conditions. parameter symbol test conditions min typ max unit isl8106
7 fn9283.1 november 10, 2006 pgnd (pin 10) the pgnd pin should be connected to the source of the bottom-side mosfet, preferably with an isolated path that is in parallel with the trace connecting the bgate pin to the gate of the mosfet. the pgnd pi n is an isolated path used exclusively to conduct the turn-o ff transient current that flows out the pgnd pin, through the gate-source capacitance of the bottom-side mosfet, into the bgate pin, and back to the pgnd pin through the pull-down resistance of the bgate driver. the adaptive shoot-through protection circuit, measures the bottom-side mosfet gate voltage with respect to the pgnd pin, not the gnd pin. bgate (pin 11) the bgate pin is the output of the bottom-side mosfet gate driver. connect to the gate of the bottom-side mosfet. the signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. route this trace in parallel with the trace from the pgnd pin. these two traces should be short, wide, and away from other traces. there should be no other weak signal traces in parallel with these traces on any layer. pvcc (pin 12) the pvcc pin is the input voltage for the bottom-side mosfet gate driver bgate. connect a +5v power source to the pvcc pin with respect to the gnd pin, a 1f mlcc bypass capacitor needs to be connected from the pvcc pin to the pgnd pin, not the gnd pin. the vcc output may be used for the pvcc input voltage source. connect the vcc pin to the pvcc pin through a low- pass filter consisting of a resistor and the pvcc bypa ss capacitor. refer to typical application schematic . boot (pin 13) the boot pin stores the input voltage for the top-side mosfet gate driver. connect an mlcc capacitor across the boot and lx pins. the boot capacitor is charged through an internal boot diode connected from the pvcc pin to the boot pin, each time the lx pin drops below pvcc minus the voltage dropped across the internal boot diode. tgate (pin 14) the tgate pin is the output of the top-side mosfet gate driver. connect to the gate of the top-side mosfet. the signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. route this trace in parallel wit h the trace from the lx pin. these two traces should be short, wide, and away from other traces. there should be no other weak signal traces in parallel with these traces on any layer. lx (pin 15) the lx pin is the return current path for the tgate mosfet driver. the lx pin also measures the polarity of the bottom-side mosfet drain voltage for the diode emulation function. connect the lx pin to the node consisting of the top-side mosfet source, the bottom-side mosfet drain, and the output inductor. refer to typical application schematic . this trace should be short, and posit ioned away from other weak signal traces. the parasitic capacitance and parasitic inductance of the lx node should be kept very low to minimize ringing. if ringing is excessive, it could easily affect current sample information. it would be best to limit the size of the lx node copper in strict accordance with the current and thermal management of the application. pgood (pin 16) the pgood pin is an open-drain output that is high impedance when the converter is in regulation, or when the en pin is pulled below the falling threshold voltage v enthf . the pgood pin has three distinct pull-down impedances that correspond to an ovp fault, ocp/scp, or uvp and soft- start. connect the pgood pin to +5v through a pull-up resistor. functional description por and soft-start the power-on reset (por) circuit monitors v cc for the v ccr (rising) and v ccf (falling) voltage thresholds. the purpose of soft-start is to limit the inrush current through the output capacitors when the converter first turns on. the pwm soft-start sequence initializes once v cc rises above the v ccr threshold, beginning from below the v ccf threshold. the isl8106 uses a digital soft-start circuit to ramp the output voltage of the converter to the programmed regulation setpoint in approximately 1.5ms. the converter regulates to 600mv at the fb pin with respect to the gnd pin. during soft-start a digitally derived voltage reference forces the converter to regulate from 0v to 600mv at the fb pin. when the en pin is pulled above the rising en threshold voltage v enthr the pgood soft-start delay t ss begins and the output voltage begins to rise. the output voltage enters regulation in approximately 1.5ms and the pgood pin goes to high impedance once t ss has elapsed. when the en pin is pulled below the v enf threshold, the ldo stops regulating and pwm immediately stops, regardless of the falling v cc voltage. the soft-start sequence can be reinitialized and fault latches reset, once v cc falls below the v ccf threshold. isl8106
8 fn9283.1 november 10, 2006 pgood the pgood pin connects to three open drain mosfets each of which has a different r ds(on) . the pgood pin is an undefined impedance if v cc has not reached the rising por threshold v ccr , or if v cc is below the falling por threshold v ccf . the isl8106 features a unique fault-identification capability that can drastically reduce trouble-shooting time and effort. the pull-down resistance of the pgood pin corresponds to the fault status of the controller. during soft- start or if an undervoltage fa ult occurs, the pgood pulldown resistance is 95 , or 30 for an overcurrent fault, or 60 for an overvoltage fault. ldo voltage applied to the vin pin with respect to the gnd pin is regulated to +5vdc by an in ternal low-dropout voltage regulator (ldo). the output of the ldo is called v cc , which is the bias voltage used by the ic internal circuitry. the ldo output is routed to the vcc pin and requires a ceramic capacitor connected to the gnd pin to stabilize the ldo and to decouple load transients. when the en pin rises above the v enr threshold, v cc will turn on and rise to its regulation voltage. the ldo regulates v cc by pulling up towards the voltage at the vin pin; the ldo has no pull-down capability. pulse width modulator the isl8106 is a hybrid of fixed frequency pwm control, and variable frequency hysteretic control. intersil?s r 3 technology can simultaneously affect the pwm switching frequency and pwm duty cycle in response to i nput voltage and output load transients. the term ?ripple? in the name ?robust-ripple- regulator? refers to the converter output inductor ripple current, not the converter output ripple voltage. the output voltage is regulated to 600mv at the fb pin with respect to the gnd pin. the fb pin is th e inverting input of the error amplifier. the frequency response of the feedback control loop is tuned with a type-t wo compensation network connected across the fb pin and comp pin. the r 3 modulator synthesizes an ac signal v r , which is an ideal representation of the output inductor ripple current. the duty-cycle of v r is derived from the voltage measured at the vin pin and vo pin with re spect to the gnd pin. transconductance amplifiers convert the vin and vo voltages into currents that charge and discharge the ripple capacitor c r . the positive slope of v r can be written as: the negative slope of v r can be written as: a voltage v w is referenced with respect to the error amplifier output voltage v comp , creating a window-voltage envelope into which voltage v r is compared. the v r, v comp, and v w signals feed into a hysteretic window comparator in which v comp is the lower threshold voltage and v w is the higher threshold voltage. pwm pulses are generated as v r traverses the v w and v comp thresholds. the charging and discharging rates of capacitor c r determine the pwm switching frequency for a given amplitude of v w with respect to v comp . the r 3 regulator simultaneously affects switching frequency and duty cycle because it modulates both edges of the pwm pulses. table 1. pgood pull-down resistance condition pgood resistance ic off open soft-start 95 undervoltage fault 95 overvoltage fault 60 overcurrent fault 30 figure 1. soft-start sequence en v out pgood 1.5ms 2.75ms v rpos gm () v in v o ? () ? = (eq. 1) v rneg gm v o ? = (eq. 2) ripple capacitor voltage c r error amplifier voltage v comp window voltage v w pwm figure 2. modulator waveforms during load transient isl8106
9 fn9283.1 november 10, 2006 mosfet gate-drivers the isl8106 has internal gate-drivers for the top-side and bottom-side n-channel mosfets. the bottom-side gate- driver is optimized for low du ty-cycle applications where the bottom-side mosfet conduction losses are dominant, requiring a low r ds(on) mosfet. the bgate pulldown resistance is small in order to clamp the gate of the mosfet below the v gs(th) at turnoff. the current transient through the gate at turnoff can be considerable because the switching charge of a low r ds(on) mosfet can be large. both drivers incorporate bottom-side mosfets from conducting simultaneously and shorting the input supply. during turn-off of the bottom-side mosfet, the bgate to pgnd voltage is monitored until it reaches a 1v threshold, at which time the tgate driver is allowed to switch. during turn-off of the top-side mosfet, the tgate to lx voltage is monitored until it reaches a 1v threshold, at which time the bgate driver is allowed to switch. the input power for the bgate driver circuit is sourced directly from the pvcc pin. the input power for the tgate driver circuit is sourced from a ?boot? capacitor connected from the boot pin to the lx pin. the boot capacitor is charged from a 5v bias supply through a internal schottky diode each time the bottom-side mosfet turns on. diode emulation positive inductor current can flow from the source of the top- side mosfet or from the drain of the bottom-side mosfet. negative inductor current flows into the drain of the bottom- side mosfet. when the bottom-side mosfet conducts positive inductor current, the lx voltage will be negative with respect to the gnd pin. conv ersely, when the bottom-side mosfet conducts negative inductor current, the lx voltage will be positive with respect to the gnd pin. negative inductor current occurs when the output load current is less than ? the inductor ripple current. the isl8106 can be configured to operate in forced- continuous-conduction-mode (fccm) or in diode-emulation- mode (dem), which can improve light-load efficiency. in fccm, the controller always operates as a synchronous rectifier, switching the botto m-side mosfet regardless of the polarity of the output indu ctor current. in dem, the bottom-side mosfet is disabled during negative current flow from the output inductor. dem is permitted when the fccm pin is pulled low, and disabled when pulled high. when dem is permitted, the converter will automatically select fccm or dem according to load conditions. if positive lx pin voltage is measured for eight consecutive pwm pulses, then the converter wi ll enter diode-emulation mode on the next pwm cycle. if a negative lx pin voltage is measured, the converter will exit dem on the following pwm pulse. an audio filter is incorporated into the pwm generation circuitry that prevents the switching frequency from entering the audible spectrum at low load conditions. overcurrent and short-circuit protection when an ocp or scp fault is detected, the isl8106 overcurrent and short-circuit protection circuit will pull the pgood pin low and latch off the converter. the fault will remain latched until the en pin is pulled below v enf or if the voltage at the vin pin is reduced to the extent that v cc has fallen below the por v ccf threshold. selecting the appropriate value of resistor r bsoc that is connected from the bsoc pin to the drain terminal of the bottom-side mosfet to programs the ocp threshold. the ocp circuit measures positive-flowing, peak-current through the output inductor, not the dc current flowing from the converter to the load. the bottom-side mosfet drain current is assumed to be equal to the positive output inductor current when the top-side mosfet is turn off. current briefly conducts through the bottom-side mosfet body diode until the bgate driver goes high. the peak inductor current develops a voltage across the r ds(on) of the bottom-side mosfet just as if it were a discrete current- sense resistor. an ocp fault will occur when the bsoc pin has measured more than the ocp threshold current i oc, on consecutive pwm pulses, for a period exceeding 20s. it does not matter how many pwm pulses are measured during the 20s period. if a measurement falls below i oc before 20s has elapsed, then the timer is reset to zero. an scp fault will occur when the bsoc pin has measured more than the short-circuit threshold current i sc, in less than 10s, on consecutive pwm pulses. the relationship between i d and i bsoc can be written as: the value of r bsoc can then be written as: figure 3. gate drive timing diagram tgate bgate t bgftgr t tgfbgr 50% 50% i bsoc r bsoc ? i d r ds on () ? = (eq. 3) r bsoc i fl i pp 2 -------- - + oc sp ? r ds on () ? i oc ---------------------------------------------------------------------------- = (eq. 4) isl8106
10 fn9283.1 november 10, 2006 where: -r bsoc ( ) is the resistor used to program the over- current setpoint -i bsoc is the current sense curr ent that is sourced from the bsoc pin -i oc is the i bsoc threshold current value sourced from the bsoc pin that will activate the ocp circuit -i fl is the maximum continuous dc load current -i pp is the inductor peak-to-peak ripple current -oc sp is the desired overcurrent setpoint expressed as a multiplier relative to i fl overvoltage when an ovp fault is detected, the isl8106 overvoltage protection circuit will pull t he pgood pin low and latch off the converter. the fault will rema in latched until the en pin is pulled below v enf or if the voltage at the vin pin is reduced to the extent that v cc has fallen below the por v ccf threshold. when the voltage at the fb pin (relative to the gnd pin) has exceeded the rising overvoltage threshold v ovr , the converter will latch off; however, the bgate driver output will stay high, forcing the bottom-side mosfet to pull down the output voltage of the converte r. the bottom-side mosfet will continue to pull down the output voltage until the voltage at the fb pin relative to the gnd pin, has decayed below the falling overvoltage threshold v ovf, at which time the bgate driver output is driven low, forcing the bottom-side mosfet off. the bgate driver output will continue to switch on at v ovr and switch off at v ovf until the en pin is pulled below v enf or if the voltage at the vin is reduced to the extent that v cc has fallen below the por v ccf threshold. undervoltage when an uvp fault is detected, the isl8106 undervoltage protection circuit will pull t he pgood pin low and latch off the converter. the uvp fault occurs when the voltage at the fb pin relative to the gnd pin, has fallen below the under- voltage threshold v uv. the fault will remain latched until the en pin is pulled below v enf or if the voltage at the vin is reduced to the extent that v cc has fallen below the por v ccf threshold. over-temperature when an otp fault is detected, the isl8106 over- temperature protection circui t suspends pwm, but will not affect the pgood pin, or latch off the converter. the over- temperature protection circuit measures the temperature of the silicon and activates when the rising threshold temperature t otr has been exceeded. the pwm remains suspended until the silicon temperature falls below the temperature hysteresis t othys at which time normal operation is resumed. all other protection circuits will function normally during otp however, since pwm is inhibited, it is likely that the converter will immediately experience an undervoltage fault, latch off, and pull pgood low. if the en pin is pulled below v enf or if the voltage at the vin is reduced to the extent that v cc has fallen below the por v ccf threshold, normal operation will resume however, the temperature hysteresis t othys is reset. application guidelines layout considerations as in any high frequency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. a multi-layer printed circuit board is recommended. figure 4 shows the critical components of the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually a middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage v out island on power plane layer island on circuit and/or power plane layer l out c out c in vin key figure 4. printed circuit board power planes and islands via connection to ground plane load q 1 q 2 c bp_vcc c bp_pvcc c in isl8106 tgate lx gnd pvcc bgate vcc boot pgnd trace sized for 4a peak current short trace, minimum impedance r vcc isl8106
11 fn9283.1 november 10, 2006 levels. keep the metal runs from the lx terminals to the output inductor short. the po wer plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the lx nodes. use the remaining printed circuit layers for small signal wiring. locate the isl8106 within 2 to 3 inches of the mosfets, q1 and q2 (1 inch or less for 500khz or higher operation). the circuit traces for the mosfets? gate and source connections from the isl8106 must be sized to handle up to 4a peak current. provide local v cc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot pin and the phase node. programming the output voltage when the converter is in regulation there will be 600mv from the fb pin to the gnd pin. connect a two-resistor voltage divider across the vo pin and the gnd pin with the output node connected to the fb pin. scale the voltage-divider network such that the fb pi n is 600mv with respect to the gnd pin when the converter is regulating at the desired output voltage. programming the output voltage can be written as: where: -v out is the desired output voltage of the converter. -v ref is the voltage that the converter regulates to at the fb pin. -r top is the voltage-programming resistor that connects from the fb pin to the vo pin. it is usually chosen to set the gain of the control-loop error amplifier. it follows that r bottom will be calculated based upon the already selected value of r top. -r bottom is the voltage-programming resistor that connects from the fb pin to the gnd pin. calculating the value of r bottom can now be written as: programming the pwm switching frequency the pwm switching frequency f osc is programmed by the resistor r fset that is connected from the fset pin to the gnd pin. programming the approximate pwm switching frequency can be written as: estimating the value of r fset can now be written as: where: -f osc is the pwm switching frequency. -r fset is the f osc programming resistor. - 60 x [1 x 10 -12 ] is a constant. selection of the lc output filter the duty cycle of a buck converte r is ideally a f unction of the input voltage and the output volt age. this relationship can be written as: where: - d is the pwm duty cycle. -v in is the input voltage to be converted. -v out is the regulated output vo ltage of the converter. the output inductor peak-to-peak ripple current can be written as: where: -i pp is the peak-to-peak output inductor ripple current. -f osc is the pwm switching frequency. -l o is the nominal value of the output inductor. a typical step-down dc/dc converter will have an i pp of 20% to 40% of the nominal dc output load current. the value of i pp is selected based upon several criteria such as mosfet switching loss, inductor core loss, and the resistance the inductor winding, dcr. the dc copper loss of the inductor can be estimated by: the inductor copper loss can be significant in the total system power loss. attention has to be give n to the dcr selection. another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. a saturated inducto r could cause destruction of circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c o into which ripple current i pp can flow. current i pp develops a corresponding ripple voltage v pp across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages can be written as: and if the output of the converter has to support a load with high pulsating current, several capacitors will need to be v ref v out r bottom r top r bottom + --------------------------------------------------- ? = (eq. 5) r bottom v ref r ? top v out v ref ? ------------------------------------- = (eq. 6) f osc 1 60 r ? fset 110 12 ? [] ? -------------------------------------------------------------- - = (eq. 7) r fset 1 60 f osc 1 12 ? 10 [] ? ? -------------------------------------------------------- = (eq. 8) dv in () v out v in --------------- - = (eq. 9) i pp v out 1dv in () ? [] ? f osc l o ? ---------------------------------------------------- - = (eq. 10) p copper i load [] 2 dcr ? = (eq. 11) v esr i pp e ? sr = (eq. 12) v c i pp 8c o f ? osc ? ---------------------------------- - = (eq. 13) isl8106
12 fn9283.1 november 10, 2006 paralleled to adjust the esr to achieve the required v pp . the inductance of the capacitor can cause a brief voltage dip when the load transient has an extremely high slew rate. low inductance capacitors constructed with reverse package geometry are available. a capacitor dissipates heat as a function of rms current. be sure that i pp is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current. take into account that the specified value of a capacitor can drop as much as 50% as the dc voltage across it increases. selection of the input capacitor the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the rms current requir ed by the switching circuit. their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. figure 5 is a graph of the input rms ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. the ripple current calculation is written as: where: -i max is the maximum continuous i load of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as: in addition to the bulk capacitance, some low esl ceramic capacitance is recommended to decouple between the drain terminal of the top-side mosfet and the source terminal of the bottom-side mosfet, in order to reduce the voltage ringing created by the switch ing current across parasitic circuit elements. mosfet selection and considerations typically, mosfets cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. the mosfets used in the power conversion stage of the converter should have a maximum v ds rating that exceeds the upper voltage tolerance of the input power source, and the voltage spike that occurs when the mosfet switches off. placing a low esr ceramic capacitor as close as practical across the drain of the top-side mosfet and the source of the bottom-side mosfet will reduce the amplitude of the turn-off voltage spike. the mosfet input capacitance c iss, and on-state drain to source resistance r ds(on) , are to an extent, inversely related; reduction of r ds(on) typically results in an increase of c iss . these two parameters affect the efficiency of the converter in different ways. the r ds(on) affects the power loss when the mosfet is completely turned on and conducting current. the c iss affects the power loss when the mosfet is actively switching. switching time increases as c iss increases. when the mosfet switches it will briefly conduct current while the drain to source voltage is still present. the power dissipation during this time is substantial so it must be kept as short as practical. often the top-side mosfet and the bottom-side mosfet are different devices due to the trade-offs that have to be made between c iss and r ds(on) . the bottom-side mosfet power loss is dominated by r ds(on) because it conducts current for the majority of the pwm switching cycle; the r ds(on) should be small. the switching loss is small for the bottom-side mosfet even though c iss is large due to the low r ds(on) of the device, because the drain to source voltage is clamped by the body diode. the top-side mosfet power loss is dominated by c iss because it conducts current for the minority of the pwm switching cycle; the c iss should be small. the switching loss of the top-side mosfet is large compared to the bottom-side mosfet because the drain to source voltage is not clamped. for the bottom-side mosfet, its power loss can be assumed to be the conduction loss only and can be written as: for the top-side mosfet, its conduction loss can be written as: (eq. 14) i in_rms i max 2 dd 2 ? () ? () xi max 2 d 12 ------ ?? ?? ?? + i max ---------------------------------------------------------------------------------------------------- - = d v out v in eff ? -------------------------- = 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 figure 5. normalized rms input current for x = 0.8 normalized input rms ripple current duty cycle x = 1 x = 0.75 x = 0.50 x = 0.25 x = 0 p conbs dv in () ? i load [] 2 r ? ds on () bs 1dv in () ? [] ? (eq. 15) p conts dv in () ? i load [] 2 r ? ds on () ts d ? v in () = (eq. 16) isl8106
13 fn9283.1 november 10, 2006 for the top-side mosfet, its switching loss can be written as: the peak and valley current of the inductor can be obtained based on the inductor peak-to-peak current and the load current. the turn-on and turn-off time can be estimated with the given gate driver parameters in the electrical specification table. selecting the bootstrap capacitor the selection of the bootstrap capacitor can be written as: where: -q g is the total gate charge required to switch the top- side mosfet - v boot , is the maximum allowed voltage decay across the boot capacitor each time the mosfet is switched on as an example, suppose the top-side mosfet has a total gate charge q g , of 25nc at v gs = 5v, and a v boot of 200mv. the calculated bootstrap capacitance is 0.125f; select at least the first standa rd component value of greater capacitance than calculated, that being 0.15f. use an x7r or x5r ceramic capacitor. compensating the converter the lc output filter has a double pole at its resonant frequency that causes the phase to abruptly roll downward. the r 3 modulator used in the isl8106 makes the lc output filter resemble a first order system in which the closed loop stability can be achieved with a type ii compensation network. figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage is regulated to the reference voltage level. the error amplifier output is compared with the oscillator triangle wave to provide a pulse-width modulated wave with an amplitude of v in at the lx node. the pwm wave is smoothed by the output filter. the output filt er capacitor bank?s equivalent series resistance is represented by the series resistor esr. p swts v in () v in i val t on f ? osc ? ? 2 ------------------------------------------------------------- v in i peak t off f ? osc ? ? 2 -------------------------------------------------------------------- - + = (eq. 17) c boot q g v boot ----------------------- - = (eq. 18) figure 6. system control block diagram + ? comp fb r comp c comp1 c comp2 r top v ref error amplifier gnd lx tgate bgate c out l out isl8106 q top_side r fset c fset q bottom_side ea + vin vin vo fb r comp r top c comp2 c comp1 - fset comp ref esr gate drivers dcr r 3 modulator figure 7. compensation reference circuit r bottom isl8106
14 fn9283.1 november 10, 2006 the control loop model of the isl8106 is partitioned into function blocks consisting of: - the duty cycle to vo transfer function g vd (s) which is determined by the value of the output power components, input voltage, and output voltage. - the vcomp to duty cycle transfer function f m (s) which is determined by the pwm frequency, input voltage, output voltage, resistor r fset , and capacitor c fset. - the product of the g vd (s) and f m (s) transfer functions is expressed as the v comp to vo transfer function g vovc (s). - the type-two compensation network g comp (s) that connects across the comp and fb pins. - the product of the g comp (s) and g vovc (s) transfer functions is expressed as the loop transfer function t(s). the compensator transfer function can be written as: where the compensator zero fz1 is the compensator pole fp1 is and the your local intersil representative can provide a pc- based tool that can be used to calculate compensation network component values and help simulate the loop frequency response. the compensation network consists of the internal error amplifier of the isl8106 and the external components r top , r comp , c comp1 , and c comp2 as well as the frequency setting components r fset , and c fset, are identified in the schematic figure 7. figure 8. system control block diagram g vovc (s) g comp (s) v comp v o v ref t(s)=g comp (s) x g vovc (s) + ? g comp s () i 1 s z1 --------- - + ? s1 s p1 ---------- + ? ---------------------------------- = (eq. 19) z1 1 r comp c comp2 ? ------------------------------------------------- = (eq. 20) f z1 z1 2 ? --------- - = (eq. 21) p1 1 c comp1 ------------------------ 1 c comp2 ------------------------ + 1 r comp --------------------- ? = (eq. 22) f p1 p1 2 ? ---------- = (eq. 23) i 1 r comp c comp1 c comp2 + [] ? ------------------------------------------------------------------------------------- - = (eq. 24) figure 9. open loop transfer function 10 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 40 20 0 20 40 60 80 100 120 150 120 90 60 30 0 30 60 90 gain (gvovc) phase (gvovc) vcomp to vo transfer function gvovc(s) frequency (hz) gain (db) phase figure 10. closed loop transfer function 10 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 40 20 0 20 40 60 80 100 120 30 15 0 15 30 45 60 75 90 gain (tv) phase (tv) voltage loop gain t(s) frequency (hz) gain (db) phase isl8106
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9283.1 november 10, 2006 isl8106 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 5 5/04 notes: 1. dimensioning and tolerances conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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